1. Technical Field
The present invention relates to a semiconductor memory apparatus and a method for driving the same, and more particularly, to a nonvolatile memory apparatus having magnetoresistive memory elements that store magnetization states as information and a method for driving the same.
2. Related Art
As portable communication devices are widely used, high performance is desired for memory elements or logic elements included in the devices. For example, high integration, high speed, and low power consumption may be preferred.
Recently, a new nonvolatile memory using a magnetic substance, magnetic random access memory (MRAM) using a tunnel magneto resistance effect, has been commercialized. Research is being conducted for higher performance as described for MRAM. MRAM changes the free direction of a free layer of a memory cell by using a magnetic field generated by an electric current flowing between a bit line and a word line. MRAM requires a predetermined switching magnetic field to drive itself. Furthermore, MRAM requires the minimum area to secure the minimum switching magnetic field. When MRAM is highly integrated, a risk of disturbance increases.
Currently, research is being conducted on spin torque transfer MRAM (STTMRAM) that provides a spin-polarized electrical current to one side and changes the direction of a free layer through spin transfer of electrons. STTMRAM can change the polarity of the free layer through spin injection for each memory cell. Thus, since a required current is reduced as the cell size decreases, STTMRAM is advantageous for high integration.
Referring to FIG. 1, STTMRAM generally includes one transistor (not illustrated) and one magnetic tunnel junction (MTJ) M. Such STTMRAM requires a reference cell to read data. In FIG. 1, BL represents a bit line, and SL represents a source line.
Referring to FIG. 2, STTMRAM may include a reference cell array separately installed on one side of a single cell array that includes a plurality of single cells where each single cell comprises one transistor and one MTJ. The reference cell array is configured to provide a reference voltage. The single cell array includes a plurality of bit lines BL. The reference cell array may be configured to include a smaller number of reference cells (not illustrated) than the number of single cells in the single cell array. Therefore, the reference cell array may occupy a small area. However, since a reference voltage having a voltage of H-L/2 that is an average of high voltage (H) and low voltage (L) is provided from the reference cell array, a sensing margin is relatively small. In FIG. 2, BLR represents a reference voltage line.
FIG. 3 illustrates another cell array having a different form from the single cell array. Referring to FIG. 3, the cell array includes bit lines BL and bit line bars BLB which are alternately arranged. When any one cell of a bit line BL is selected, a corresponding cell of a bit line bar BLB having a complementary relation with the bit line BL is used as a reference cell. Such a structure is referred to as a twin cell structure.
In the twin cell structure, a difference between a voltage (for example, H) applied to the bit line and a voltage (for example, L) applied to the bit line bar during a data read operation becomes a sensing margin (H-L). Therefore, the twin cell structure has a sensing margin two times larger than that of the single cell array. However, since a reference line (reference cell) should be provided at every bit line, the area of the twin cell structure becomes two times larger than that of the single cell array.